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datasheet AX5243 advanced high performance ask and fsk narrow - band transceiver for 27 - 1050 mhz range revision 2
www.onsemi.com AX5243 2 table of contents 1. overview ................................ ................................ ................................ ..... 5 1.1. features ................................ ................................ ................................ ....... 5 1.2. applications ................................ ................................ ................................ .. 6 2. bl ock diagram ................................ ................................ ............................. 7 3. pin function descriptions ................................ ................................ ........... 8 3.1. pinout drawing ................................ ................................ .............................. 9 4. specifications ................................ ................................ ............................ 10 4.1. absolute maximum ratings ................................ ................................ ............ 10 4.2. dc characteristics ................................ ................................ ........................ 11 supplies ................................ ................................ ................................ ....... 11 logic ................................ ................................ ................................ ........... 13 4.3. ac characteristics ................................ ................................ ......................... 14 crystal oscillator ................................ ................................ ........................... 14 low - power oscillator ................................ ................................ ..................... 14 rf frequency generation subsystem (synthesizer) ................................ ........... 15 transmitter ................................ ................................ ................................ .. 18 receiver sensitivities ................................ ................................ ..................... 19 receiver ................................ ................................ ................................ ...... 19 receiver and transmitter settling phases ................................ ......................... 21 overall state transition times ................................ ................................ ........ 22 spi timing ................................ ................................ ................................ ... 22 general purpose adc (gpadc) ................................ ................................ ....... 23 5. circuit description ................................ ................................ .................... 24 5.1. voltage regu lators ................................ ................................ ....................... 25 5.2. crystal oscillator and tcxo interface ................................ .............................. 26 5.3. low power oscillator and wake on radio (wor) mode ................................ ...... 26
table of contents w ww.onsemi.com AX5243 3 5.4. gpio pin ................................ ................................ ................................ ...... 27 5.5. sysclk output ................................ ................................ ............................ 27 5.6. power - on - reset (por) ................................ ................................ ................... 28 5.7. rf frequency generation subsystem ................................ .............................. 28 vco ................................ ................................ ................................ ............ 28 vco auto - ranging ................................ ................................ ........................ 29 loop filter and charge pump ................................ ................................ .......... 29 registers ................................ ................................ ................................ ..... 30 5.8. rf input and output stage (antp/antn) ................................ ........................ 31 lna ................................ ................................ ................................ ............. 31 pa ................................ ................................ ................................ ............... 31 5.9. digital if channel filter and demodulator ................................ ........................ 31 registers ................................ ................................ ................................ ..... 32 5.10. encoder ................................ ................................ ................................ ... 33 5.11. framing and fifo ................................ ................................ ..................... 33 packet modes ................................ ................................ ............................... 34 raw modes ................................ ................................ ................................ .. 35 5.12. rx agc and rssi ................................ ................................ ..................... 35 5.13. modulator ................................ ................................ ................................ 36 5.14. automatic frequency control (afc) ................................ ............................ 36 5.15. pwrmode register ................................ ................................ ................... 37 5.16. serial peripheral interface (spi) ................................ ................................ . 39 spi timing ................................ ................................ ................................ ... 40 5.17. general purpose adc (gpadc) ................................ ................................ ... 41 ????? ?? dac ................................ ................................ ................................ ........ 41 6. register bank description ................................ ................................ ......... 42 6.1. control register map ................................ ................................ ..................... 43 7. application information ................................ ................................ ............ 55 7.1. typical application diag rams ................................ ................................ .......... 55
table of contents www.onsemi.com AX5243 4 match to 50 ohm for the antenna pins (868/915/433/169 mhz rx/tx operation) . 55 using a dipole antenna and the internal tx /rx switch ................................ ...... 56 using a single - ended antenna and the internal tx/rx switch ............................. 57 using an external vco inductor ................................ ................................ ...... 58 using an external vco ................................ ................................ ................... 59 using a tcxo ................................ ................................ ............................... 60 8. qfn28 package information ................................ ................................ ..... 61 8.1. package outline qfn20 4 mm x 4 mm ................................ ............................ 61 8.2. qfn28 soldering profile ................................ ................................ ................. 62 8.3. qfn28 recommended pad layout ................................ ................................ .. 63 8.4. assembly process ................................ ................................ ......................... 63 stencil design & solder paste application ................................ ......................... 63
table of contents w ww.onsemi.com AX5243 5 1. overview 1.1. features advanced multi - channel narrow - band single chip uhf transceiver (fsk/msk/4 - fsk/gfsk/gmsk/ ask/afsk/fm/psk) low - power ? rx 9.5 ma @ 868 mhz and 433 mhz 6.5 ma @ 169 mhz ? tx at 868 mhz 7.5 ma @ 0 dbm 16 ma @ 10 dbm 48 ma @ 16 dbm ? 50 na deep sleep current ? 500 na power - down current with low frequency duty cycle clock running extended supply voltage range ? 1.8 v - 3.6 v single supply high sensitivity / high selectivity receiver ? data rates from 0.1 kbps to 125 kbps ? optional f orward error correction (fec) ? sensitivity without fec C 135 dbm @ 0.1 kbps, 868 mhz, fsk C 126 dbm @ 1 kbps, 868 mhz, fsk C 117 dbm @ 10 kbps, 868 mhz, fsk C 107 dbm @ 100 kbps, 868 mhz, fsk C 105 dbm @ 125 kbps, 868 mhz, fsk C 138 dbm @ 0.1 kbp s, 868 mhz, psk C 130 dbm @ 1 kbps, 868 mhz, psk C 120 dbm @ 10 kbps, 868 mhz, psk C 109 dbm @ 100 kbps, 868 mhz, psk C 108 dbm @ 125 kbps, 868 mhz, psk ? sensitivity with fec C 137 dbm @ 0.1 kbps, 868 mhz, fsk C 122 dbm @ 5 kbps, 868 mhz, fsk C 111 db m @ 50 kbps, 868 mhz, fsk ? high selectivity receiver with up to 45 db adjacent channel rejection ? 0 dbm maximum input power ? > +/ - 10% data - rate error tolerance ? short preamble modes allow the receiver to work with as little as 16 preamble bits ? fast state swi tching times 200 ? ? ? ? transmitter ? data - rates from 0.1 kbps to 125 kbps ? high efficiency, high linearity integrated power amplifier ? maximum output power 16 dbm @ 868 mhz 16 dbm @ 433 mhz 16 dbm @ 169 mhz ? p ower level programmable in 0.5 db steps ? gfsk shaping with bt=0.3 or bt=0.5 ? unrestricted power ramp shaping frequency generation ? configurable for usage in 27 mhz C 1050 mhz bands ? rf carrier frequency and fsk deviation programmable in 1 hz steps ? ultra fast settling rf frequency synthesizer for low - power consumption ? fully integrated rf frequency synthesizer with vco auto - ranging and band - width boost modes for fast locking ? configurable for either fully integrated vco, internal vco with external inductor or fu lly external vco ? configurable for either fully integrated or external synthesizer loop filter for a large range of bandwidths ? channel hopping up to 2000 hops/s ? automatic frequency control (afc) flexible antenna interface ? integrated rx/tx switching with d ifferential antenna pins wakeup - on - radio ? 640 hz or 10 khz lowest power wake - up timer ? wake - up time interval programmable between 98 ?
overview www.onsemi.com AX5243 6 sophisticated radio controller ? fully automatic packet reception and transmission without micro - controller i ntervention ? supports hdlc, raw, wireless m - bus frames and arbitrary defined frames ? automatic channel noise level tracking ? ? s resolution timestamps for exact timing (e.g. for frequency hopping systems) ? 256 byte micro - programmable fifo, optionally supports p acket sizes > 256 bytes ? 3 matching units for preamble byte, sync - word and address ? ability to store rssi, frequency offset and data - rate offset with the packet data ? multiple receiver parameter sets allow the use of more aggressive receiver parameters during preamble, dramatically shortening the required preamble length at no sensitivity degradation advanced crystal oscillator ? fast start - up and lowest power steady - state xtal oscillator for a wide range of crystals ? integrated crystal tuning capacitors ? possibi lity of applying an external clock reference (tcxo) miscellaneous features ? few external components ? spi microcontroller interface ? extended axsem register set ? fully integrated current/voltage references ? qfn20 4 mm x 4 mm package ? internal power - on - reset ? brow n - out detection ? 10 bit 1ms/s general purpose adc (gpadc) 1.2. applications 27 C 1050 mhz licensed and unlicensed radio systems. ? internet of things ? automatic meter reading (amr) ? security applications ? building automation ? wireless networks ? messaging paging ? com patible with: wireless m - bus, pocsag, flex, knx, sigfox, z - wave, enocean ? regulatory regimes: en 300 220 v2.3.1 including the narrow - band 12.5 khz, 20 khz and 25 khz definitions; en 300 422; fcc part 15.247; fcc part 15.249; fcc part 90 6.25 khz, 12.5 khz a nd 25 khz
block diagram w ww.onsemi.com AX5243 7 2. block diagram figure 1 functional block diagram of the AX5243 AX5243 3 antp 4 antn if filter & agc pgas agc crystal oscillator typ. 16 mhz f out f xtal communication controller & serial interface divider adc digital if channel filter lna pa diff de - modulator encode r framing fifo modulator mixer 20 clk16p 19 clk16n chip configuratio n 9 sysclk vdd_io voltage regulator s por low power oscillator 640 hz/10khz forward error correction 17 gpadc1 18 gpadc2 6 filt 7 l1 8 l2 vdd_ana 10 sel 11 clk 12 miso 13 mosi 14 irq 15 tcxo_en 1,5 16 radio controller timing and packet handling references wake on radio registers spi rf frequency generation subsystem rf output 27 mhz C 1.05 ghz fifo
pin function descriptions www.onsemi.com AX5243 8 3. pin function descriptions symbol pin(s) type description vdd_ana 1 p analog power output, decouple to neighboring gnd gnd 2 p ground, decouple to neighboring vdd_ana antp 3 a differential antenna input/output antn 4 a differential antenna input/output vdd_ana 5 p analog power output, decouple to gnd filt 6 a optional synthesizer filter l2 7 a optional synthesizer inductor, should be shorted with l1 if not used. l1 8 a optional synthesi zer inductor, should be shorted with l2 if not used. sysclk 9 i/o default functionality: crystal oscillator (or divided) clock output can be programmed to be used as a general purpose i/o pin selectable internal 65 k ? pull - up resistor sel 10 i serial per ipheral interface select clk 11 i serial peripheral interface clock miso 12 o serial peripheral interface data output mosi 13 i serial peripheral interface data input irq 14 i/o default functionality: transmit and receive interrupt can be programme d to be used as a general purpose i/o pin selectable internal 65 k ? pull - up resistor tcxo_en 15 i/o general purpose i/o pin which can be programmed to enable an external tcxo selectable internal 65 k ? pull - up resistor vdd_io 16 p power supply 1.8 v C 3.3 v gpadc1 17 a gpadc input, must be connected to gnd if not used gpadc2 18 a gpadc input, must be connected to gnd if not used clk16n 19 a crystal oscillator input/output clk16p 20 a crystal oscillator input/output gnd center pad p ground on center pad of qfn, must be connected a = analog signal i/o = digital input/output signal i = digital input signal n = not to be connected o = digital output signal p = power or ground all digital inputs are schmitt trigger inputs, digital input and output levels are lvcmos/lvttl compatible and 5v tolerant .
pin function descriptions w ww.onsemi.com AX5243 9 3.1. pinout drawing exposed centre pad of the qfn package: gnd figure 2 : pinout drawing (top view) 1 2 3 4 5 vdd _ana gnd antn vdd_ana antp miso mosi 11 15 14 13 12 ir q tcxo_en clk 9 10 8 7 6 filt l2 l1 sysclk sel 19 16 18 17 20 clk16 p gpadc1 clk16n gpadc2 vdd_io AX5243
specifications www.onsemi.com AX5243 10 4. specifications 4.1. absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol description condition min max unit vdd_io supply voltage - 0.5 5.5 v idd supply current 200 ma p tot total power consumption 800 mw p i absolu te maximum input power at receiver input antp and antn pins in rx mode 10 dbm i i1 dc current into any pin except antp, antn - 10 10 ma i i2 dc current into pins antp, antn - 100 100 ma i o output current 40 ma v ia input voltage antp, antn pins - 0.5 5 .5 v input voltage digital pins - 0.5 5.5 v v es electrostatic handling hbm - 2000 2000 v t amb operating temperature - 40 85 c t stg storage temperature - 65 150 c t j junction temperature 150 c
specifications w ww.onsemi.com AX5243 11 4.2. dc characteristics supplies symbol description cond ition min typ max unit t amb operational ambient temperature - 40 27 85 c vdd_io i/o and voltage regulator supply voltage 1.8 3.0 3.6 v v bout brown - out threshold note 1 1.3 v i dsleep deep - sleep current: all analog and digital functions are powered d own pwrmode=0x01 50 na i pdown power - down current: register file contents preserved pwrmode=0x00 400 na i wor wakeup - on - radio mode: low power timer and wor state - machine are running at 640 hz pwrmode=0x0b 500 na ? i standby standby - current: all power domains are powered up, crystal oscillator and references are running. pwrmode=0x05 230 a i rx current consumption rx pwrmode=0x09 rf frequency subsystem: internal vco and internal loop - filter 868 mhz, datarate 6 kbps 9.5 ma 169 mhz, datarate 6 kbps 6.5 868 mhz, datarate 100 kbps 11 169 mhz, datarate 100 kbps 7.5 i tx - di ff current consumption tx 868 mhz, 16 dbm, fsk, note 2, rf frequency subsystem: internal vco and loop - filter 48 ma notes: 1. digital circuitry is functional down to typically 1 v. 2. measured with optimized matching networks. for information on curr ent consumption in complex modes of operation tailored to your application, see the software ax - radiolab for AX5243 .
specifications www.onsemi.com AX5243 12 note on current consumption in tx mode to achieve best output power the matching network has to be optimized for the desired output power and frequency. as a rule of thumb a good matching network produces about 50% efficiency with the AX5243 power amplifier although over 90% are theoretically possible. a typical ma tching network has between 1 db and 2 db loss (p loss ). the pa is internally multiplexed with the lna on pins antp and antn. therefore constraints for the rx matching have to be considered for the pa matching. the current consumption can be calculated as i tx [ma]=1/pa efficiency *10^((p out [dbm]+p loss [db])/10)/1.8v+i offset i offset is about 6 ma for the fully integrated vco at 400 mhz to 1050 mhz, and 3 ma for the vco with external inductor at 169 mhz. the following table shows calculated current consumptions ve rsus output power for p loss = 1 db, pa efficiency = 0.5, i offset = 6 ma at 868 mhz and i offset = 3.5 ma at 169 mhz pout [dbm] i txcalc [ma] 868 mhz 169 mhz 0 7.5 4.5 1 7.9 4.9 2 8.4 5.4 3 9.0 6.0 4 9.8 6.8 5 10.8 7.8 6 12.1 9.1 7 13.7 10.7 8 15.7 12 .7 9 18.2 15.2 10 21.3 18.3 11 25.3 22.3 12 30.3 27.3 13 36.7 33.7 14 44.6 41.6 15 54.6 51.6 both AX5243 power amplifiers run from the regulated vdd_ana supply and not directly from the battery. this has the a dvantage that the current and output power do not vary much over supply voltage and temperature.
specifications w ww.onsemi.com AX5243 13 logic symbol description condition min typ max unit digital inputs v t+ schmitt trigger low to high threshold point 1.9 v v t - schmitt trigger high to low threshold point 1.2 v v il input voltage, low 0.8 v v ih input voltage, high 2.0 v i l input leakage current - 10 10 a r pullup pull - up resistors pins sysclk, irq, tcxo_en pull - ups enabled in the relevant pin configuration registers 65 k d igital outputs i oh output current, high vdd_io=3 v v oh = 2.4 v 4 ma i ol output current, low vdd_io=3 v v ol = 0.4 v 4 ma i oz tri - state output leakage current - 10 10 a
specifications www.onsemi.com AX5243 14 4.3. ac characteristics crystal oscillator symbol description condition min typ max u nit f xtal crystal frequency notes 1, 2, 3 10 16 50 mhz gm osc oscillator transconductance control range self - regulated see note 4 0.2 20 ms c osc programmable tuning capacitors at pins clk16n and clk16p xtalcap = 0x00 default 3 pf xtalcap = 0x01 8 .5 pf xtalcap = 0xff 40 pf c osc - lsb programmable tuning capacitors, increment per lsb of xtalcap xtalcap = 0x01 C 0xff 0.5 pf f ext external clock input (tcxo) notes 2, 3, 5 10 16 50 mhz rin osc input dc impedance 10 k ndiv sysclk divider ratio f sysclk = f xtal / ndiv sysclk 2 0 2 4 2 10 notes 1. tolerances and start - up times depend on the crystal used. depending on the rf frequency and channel spacing the ic must be calibrated to the exact crystal frequency using the re adings of the register trkfreq 2. the choice of crystal oscillator or tcxo frequency depends on the targeted regulatory regime for tx, see separate documentati on on meeting regulatory requirements. 3. to avoid spurious emission, the crystal or tcxo reference fre quency should be chosen so that the rf carrier frequency is not an integer multiple of the crystal or tcxo frequency. 4. the oscillator transconductance is regulated for fastest start - up time during start - up and for lowest power during steady state oscillatio n. this means that values will depend on the crystal used. 5. if an external clock (tcxo) is used, it should be input via an ac coupling at pin clk16p with the oscillator powered up and xtalcap=0x00. for detailed tcxo network recommendations depending on tcxo output swing refer to the AX5243 application note: use with a txco reference clock. low - power oscillator symbol description condition min typ max unit f osc - slow oscillator frequency slow mode lposc fast=0 no cali bration 480 640 800 hz internal calibration vs. crystal clock has been performed 630 640 650 hz f osc - fast oscillator frequency fast mode lposc fast=1 no calibration 7.6 10.2 12.8 khz internal calibration vs. crystal clock has been performed 9.8 10.2 10.8 khz
specifications w ww.onsemi.com AX5243 15 rf frequency generation subsystem (synthesizer) sym description condition min typ max unit f ref reference frequency the reference frequency must be chosen so that the rf carrier frequency is not an integer multiple of the reference frequency 10 16 50 mhz dividers ndiv ref reference divider ratio range controlled directly with register refdiv 2 0 2 3 ndiv m main divider ratio range controlled indirectly with register freq 4.5 66.5 ndiv rf rf divider range controlled directly with register r fdiv 1 2 charge pump i cp charge pump current programmable in increments of 8.5 a via register pllcpi 8.5 2168 a internal vco (vcosel=0) f rf rf frequency range rfdiv=1 400 525 mhz rfdiv=0 800 1050 f step rf frequency step rfdiv=1, fxtal=16.000000 mhz 0.98 hz bw synthesizer loop bandwidth the synthesizer loop bandwidth and start - up time can be programmed with registers pllloop and pllcpi. for recommendations see the AX5243 programming manual, the ax - radiolab software and AX5243 application notes on compliance with regulatory regimes. 50 5 00 khz t start synthesizer start - up time if crystal oscillator and reference are running 5 25 s pn868 synthesizer phase noise 868 mhz f ref = 48 mhz 10 khz offset from carrier - 95 dbc/hz 1 mhz offset from carrier - 120 pn433 synthesizer phase noise 433 mhz f ref = 48 mhz 10 khz offset from carrier - 105 dbc/hz 1 mhz offset from carrier - 120 vco with external inductors (vcosel=1, vco2int=1) f rfrng_lo rf frequency range for choice of l ext values as well as vco gains see figure 3 and figure 4 rfdiv=1 27 262 mhz f rfrng_hi rfdiv=0 54 525 pn169 synthesizer phase noise 169 mhz l ext =47 nh (wire wound 0603) rfdiv=0, f ref = 16 mhz note: phase noises can be improved with higher f ref 10 khz from carrier - 97 dbc/hz 1 mhz from carrier - 115 external vco (vcosel=1, vco2int=0) f rf rf frequency range fully external vco note: the external vco frequency needs to be 2xf rf 27 1000 mhz v amp differential input amplitude at l1, l2 terminals 0.7 v v inl input voltage levels at l1, l2 terminals 0 1.8 v v ctrl control voltage range availa ble at terminal filt in external loop filter mode 0 1.8 v
specifications www.onsemi.com AX5243 16 figure 3 vco with external inductors: typical frequency vs l ext figure 4 vco with exter nal inductors: typical k vco vs l ext
specifications w ww.onsemi.com AX5243 17 the following table shows the typical frequency ranges for frequency synthesis with external vco inductor for different inductor values. lext [nh] freq [mhz] freq [mhz] pll range rfdiv=0 rfdiv = 1 8.2 482 241 0 8. 2 437 219 15 10 432 216 0 10 390 195 15 12 415 208 0 12 377 189 15 15 380 190 0 15 345 173 15 18 345 173 0 18 313 157 15 22 308 154 0 22 280 140 14 27 285 143 0 27 258 129 15 33 260 130 0 33 235 118 15 39 245 123 0 39 223 112 14 47 212 106 0 47 194 97 14 56 201 101 0 56 182 91 15 68 178 89 0 68 161 81 15 82 160 80 1 82 146 73 14 100 149 75 1 100 136 68 14 120 136 68 0 120 124 62 14 for tuning or changing of ranges a capacitor can be added in parallel to the inductor.
specifications www.onsemi.com AX5243 18 transmitte r symbol description condition min typ max unit sbr signal bit rate 0.1 125 kbps ptx transmitter power @ 868 mhz differential pa, 50 ? single ended measurement at an sma connector behind the matching network, note 2 - 10 16 dbm transmitter power @ 433 mhz - 10 16 transmitter power @ 169 mhz - 10 16 ptx 868 - step programming step size output power note 1 0.5 db dptx temp transmi tter power variation vs. temperature - 40 c to +85 c note 2 +/ - 0.5 db dptx vdd transmitter power variation vs. vdd_io 1.8 v to 3.6 v note 2 +/ - 0.5 db padj adjacent channel power gfsk bt=0.5, 500 hz deviation, 1.2kbps, 25 khz channel spacing, 10 kh z channel bw 868 mhz - 44 dbc 433 mhz - 51 ptx 868 - harm2 emission @ 2 nd harmonic 868 mhz, note 2 - 40 dbc ptx 868 - harm3 emission @ 3 rd harmonic - 60 ptx 433 - harm2 emission @ 2 nd harmonic 433 mhz, note 2 - 40 dbc ptx 433 - harm3 emission @ 3 rd har monic - 40 notes 1. 2. 50 ? single ended measurements at an sma connector behind the matching network . for recommended matching networks see section 7 : applicat ion information . max 12 1 2 p b txpwrcoeff p out ? ? ?
specifications w ww.onsemi.com AX5243 19 receiver sensitivities the table lists typical input sensitivities (without fec) in dbm at the sma connector with the complete matching network for ber=10 - 3 at 433 or 868 mhz. data rate [kbps] fsk h=0.66 fsk h=1 fsk h=2 f sk h=4 fsk h=5 fsk h=8 fsk h=16 psk 0.1 sensitivity [dbm] - 135 - 134.5 - 132.5 - 133 - 133.5 - 133 - 132.5 - 138 rx bandwidth [khz] 0.2 0.2 0.3 0.5 0.6 0.9 2.1 0.2 deviation [khz] 0.033 0.05 0.1 0.2 0.25 0.4 0.8 1 sensitivity [dbm] - 126 - 125 - 123 - 123.5 - 124 - 123.5 - 122.5 - 130 rx bandwidth [khz] 1.5 2 3 6 7 11 21 1 deviation [khz] 0.33 0.5 1 2 2.5 4 8 10 sensitivity [dbm] - 117 - 116 - 113 - 114 - 113.5 - 113 - 120 rx bandwidth [khz] 15 20 30 50 60 110 10 deviation [khz] 3.3 5 10 20 25 40 100 se nsitivity [dbm] - 107 - 105.5 - 109 rx bandwidth [khz] 150 200 100 deviation [khz] 33 50 125 sensitivity [dbm] - 105 - 104 - 108 rx bandwidth [khz] 187.5 200 125 deviation [khz] 42.3 62.5 notes 1. sensitivities are equi valent for 1010 data streams and pn9 whitened data streams. 2. rx bandwidths < 0.9 khz cannot be achieved with an 48 mhz tcxo. a 16 mhz tcxo was used for all measurements at 0.1 kbps. receiver sym description condition min typ max unit sbr signal bit rate 0.1 125 kbps is ber868 input sensitivity at ber = 10 - 3 for 868 mhz operation, continuous data, without fec fsk, h = 0.5, 100 kbps - 105 dbm fsk, h = 0.5, 10 kbps - 116 fsk, 500 hz deviation, 1.2 kbps - 126 psk, 100 kbps - 109 psk, 10 0 kbps - 120 psk, 100 kbps - 130
specifications www.onsemi.com AX5243 20 sym description condition min typ max unit is ber868fec input sensitivity at ber = 10 - 3 for 868 mhz operation, continuous data, with fec fsk, h = 0.5, 50 kbps - 111 dbm fsk, h = 0.5, 5 kbps - 122 fsk, 0.1 kbps - 137 is per868 input sensitivity at per = 1% for 868 mhz operation, 144 bit packet data, without fec fsk, h = 0.5, 100 kbps - 103 dbm fsk, h = 0.5, 10 kbps - 115 fsk, 500 hz deviation, 1.2 kbps - 125 is wor868 input sensitivity at per = 1% for 868 mhz operation, 144 bit packet d ata, wor - mode, without fec fsk, h = 0.5, 100 kbps - 102 dbm il maximum input level 0 dbm cp 1db input referred compression point 2 tones separated by 100 khz - 35 dbm rssir rssi control range fsk, 500 hz deviation, 1.2 kbps - 126 - 46 db rssis 1 rs si step size before digital channel filter; calculated from register agccounter 0.625 db rssis 2 rssi step size behind digital channel filter; calculated from registers agccounter, trkampl 0.1 db rssis 3 rssi step size behind digital channel filter; re ading register rssi 1 db sel 868 adjacent channel suppression 25 khz channels note 1 45 db 100 khz channels note 1 47 blk 868 blocking at +/ - 10 mhz offset fsk 4.8 kbps, note 2 78 db r afc afc pull - in range the afc pull - in range can be prog rammed with the maxrfoffset registers. the afc response time can be programmed with the freqgaind register. +/ - 15 % r droff bitrate offset pull - in range the bitrate pull - in range can be programmed with the maxdroffset registers. +/ - 10 % notes 1. interf erer/channel @ ber = 10 - 3 , channel level is +3 db above the typical sensitivity, the interfering signal is cw; channel signal is modulated with shaping 2. channel/blocker @ ber = 10 - 3 , channel level is +3 db above the typical sensitivity, the blocker signal is cw; channel signal is modulated with shaping
specifications w ww.onsemi.com AX5243 21 receiver and transmitter settling phases symbol description condition min typ max unit t xtal xtal settling time powermodes: powerdown to standby note that t xtal depends on the specific crystal used. 0.5 ms t synth synthesizer settling time powermodes: standby to synthtx or synthrx 40 s t tx tx settling time powermodes: synthtx to fulltx t tx is the time used for power ramping, this can be programmed to be 1 x t bit , 2 x t bit , 4 x t bit or 8 x t bit . not e 1, 2 0 1 x t bit 8 x t bit s t rx_init rx initialization time 150 s t rx_rssi rx rssi acquisition time (after t rx_init ) powermodes: synthrx to fullrx modulation (g)fsk note 1, 2 80 + 3 x t bit s t rx_preamble rx signal acquisition time to valid data rx at full sensitivity/selectivity (after t rx_init ) 9 x t bit notes 1. t bit depends on the datarate, e.g. for 10 kbps t bit = 100 s 2. in wire mode there is a processing delay of typically 6 x t bit between antenna and dclk/data pins
specifications www.onsemi.com AX5243 22 overall state tra nsition times symbol description condition min typ max unit t tx_on tx startup time powermodes: standby to fulltx note 1, 2 40 40 + 1 x t bit s t rx_on rx startup time powermodes: standby to fullrx 190 s t rx_rssi rx startup time to valid rssi powermo des: standby to fullrx modulation (g)fsk note 1, 2 270 + 3 x t bit s t rx_data rx startup time to valid data at full sensitivity/selectivity 190 + 9 x t bit s t rxtx rx to tx switching powermodes: fullrx to fulltx 62 s t txrx tx to rx switchin g (to preamble start) powermodes: fulltx to fullrx 200 t hop frequency hop switch between frequency defined in register freqa and freqb 30 s notes 1. t bit depends on the datarate, e.g. for 10 kbps t bit = 100 s 2. in wire mode there is a processing del ay of typically 6 x t bit between antenna and dclk/data pins spi timing symbol description condition min typ max unit tss sel falling edge to clk rising edge 10 ns tsh clk falling edge to sel rising edge 10 ns tssd sel falling edge to miso driving 0 10 ns tssz sel rising edge to miso high - z 0 10 ns ts mosi setup time 10 ns th mosi hold time 10 ns tco clk falling edge to miso output 10 ns tck clk period note 1 50 ns tcl clk low duration 40 ns tch clk high duration 40 ns notes 1. for spi access during power - down mode the period should be relaxed to 100 ns. for a figure showing the spi timing parameters see section 5.16 : serial peripheral interface (spi) .
specifications w ww.onsemi.com AX5243 23 general purpose adc (gpadc) symbol description condition min typ max unit res nominal adc resolution 10 bit f conv conversion rate 0.03 1 ms/s dr dynamic range 60 db inl integral nonlinearity +/ - 1 lsb dnl differential nonlinearity +/ - 1 lsb z in input impedance 50 k v dc - in input dc level 0.8 v v in - diff input signal range (differential) - 500 500 mv v in - se input signal range (single - ended, signal input at pin gpadc1, pin gpadc2 open) 300 1300 mv
circuit description www.onsemi.com AX5243 24 5. circuit description the AX5243 is a true single chip ultra - low power narrow - band cmos transceiver for use in licensed and unlicensed bands from 27 and 1050 mhz. the on - chip transceiver consists of a fully integrated rf front - end with modulator, and demodulator . base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the spi interface. AX5243 can be operated from a 1.8 v to 3.6 v power supply over a temperature range of - 40 o c to 85 o c. it consumes 7 - 48 ma for transmitting at 868 mhz carrier frequency, 4 C 51 ma for transmitting at 169 mhz depending on the output power. in receive operation AX5243 consume s 9 - 11 ma at 868 mhz carrier frequency and 6.5 - 8.5 ma at 169 mhz. the AX5243 features make it an ideal interface for integration into various battery powered solutions such as ticketing or as transceiver for tele metric applications e.g. in sensors. as primary application, the transceiver is intended for uhf radio equipment in accordance with the european telecommunication standard institute (etsi) specification en 300 220 - 1 and the us federal communications commis sion (fcc) standard title 47 cfr part 15 as well as part 90. AX5243 is compliant with the respective narrow - band regulations. additionally AX5243 is suited for systems targeting compliance with wireless m - bus standard en 13757 - 4:2005. wireless m - bus frame support (s, t, r) is built - in. AX5243 supports any data rate from 0.1 kbps to 125 kbps for fsk, 4 - fsk, gfsk, gmsk, msk, ask and psk. to ac hieve optimum performance for specific data rates and modulation schemes several register settings to configure the AX5243 are necessary, for details see the axsem radiolab software which calculates the necessary regi ster settings and the AX5243 programming manual . the AX5243 can be operated in two fundamentally different modes. data is sent and received via the spi port in frames. pre - and post - ambles as well as checksums can be generated automatically. interrupts control the data flow between a micro - controller and the AX5243 . both transmit and receive use frame mode. in both cases the AX5243 behaves as a spi slave interface. configuration of the AX5243 is always done via the spi interface. the receiver and the transmitter support multi - channel operation for all data rates a nd modulation schemes.
circuit description w ww.onsemi.com AX5243 25 5.1. voltage regulators the AX5243 uses an on - chip voltage regulator system to create stable supply voltages for the internal circuitry from the primary supply vdd_io. the i/o level of the digital pi ns is vdd_io. pins vdd_ana are supplied for external decoupling of the power supply used for the on - chip pa. the voltage regulator system must be set into the appropriate state before receive or transmit operations can be initiated. this is handled autom atically when programming the device modes via the pwrmode register. register powstat contains status bits that can be read to check if the regulated voltages are ready (bit svio) or if vdd_io has dropped below the brown - out level of 1.3v (bit ssum). in p ower - down mode the core supply voltages for digital and analog functions are switched off to minimize leakage power. most register contents are preserved but access to the fifo is not possible and fifo contents are lost. spi access to registers is possible , but at lower speed. in deep - sleep mode all supply voltages are switched off. all digital and analog functions are disabled. all register contents are lost. to leave deep - sleep mode the pin sel has to be pulled low. this will initiate startup and reset of the AX5243 . then the miso line should be polled, as it will be held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation.
circuit description www.onsemi.com AX5243 26 5.2. crystal oscillator and tcxo interface the AX5243 is normally operated with an external tcxo, which is required by most narrow - band regulation with a tolerance of 0.5 ppm to 1.5 ppm depending on the regulation. the on - chip crystal oscillato r allows the use of an inexpensive quartz crystal as the rf generation subsystems timing reference when possible from a regulatory point of view. a wide range of reference frequencies can be handled by the crystal oscillator circuit. as the reference fre quency impacts both the spectral performance of the transmitter as well as the current consumption of the receiver, the choice of reference frequency should be made according to the regulatory regime targeted by the application. for guide - lines see the sep arate application notes for usage of AX5243 in compliance with various regulatory regimes. the crystal or tcxo reference frequency should be chosen so that the rf carrier frequency is not an integer multiple of the cr ystal or tcxo frequency. the oscillator circuit is enabled by programming the pwrmode register. at power - up it is enabled. to adjust the circuits characteristics to the quartz crystal being used, without using additional external components, the tuning ca pacitance of the crystal oscillator can be programmed. the transconductance of the oscillator is automatically regulated, to allow for fastest start - up times together with lowest power operation during steady - state oscillation. the integrated programmable tuning capacitor bank makes it possible to connect the oscillator directly to pins clk16n and clk16p without the need for external capacitors. it is programmed using bits xtalcap[5:0] in register xtalcap . to synchronize the receiver frequency to a carrier signal, the oscillator frequency could be tuned using the capacitor bank however, the recommended method to implement frequency synchronization is to make use of the high resolution rf frequency generation sub - system together with the automatic frequency control, both are described further down. alternatively a single ended reference (txco, cxo) may be used. for detailed tcxo network recommendations depending on tcxo output swing refer to the AX5243 application note: use with a txco reference clock. 5.3. low power oscillator and wake on radio (wor) mode the AX5243 features an internal lowest power fully integrated oscillator. in default mode the frequency of oscillation is 640 hz +/ - 1 .5%, in fast mode it is 10.2 khz +/ - 1.5%. these accuracies are reached after the internal hardware has been used to calibrate the low power oscillator versus the rf reference clock. this procedure can be run in the background during transmit or receive o perations. the low power oscillator makes a wor mode with a power consumption of 500na possible.
circuit description w ww.onsemi.com AX5243 27 if wake - on - radio mode is enabled, the receiver wakes up periodically at a user selectable interval, and checks for a radio signal on the selected channel. if no signal is detected, the receiver shuts down again. if a radio signal is detected, and a valid packet is received, the micro - controller is alerted by asserting an interrupt. the AX5243 can thus autonomously poll for radio signals, while the micro - controller can stay powered down, and only wakes up once a valid packet is received. this allows for very low average receiver power, at the expense of longer preambles at the transmitter. 5.4. gpio pin pins sysclk, irq and tcxo _en can be used as general purpose i/o pins by programming pin configuration registers pinfuncsysclk , pinfuncirq , pinfuncpwramp . pin input values can be read via register pinstate . pull - ups are disabled if output data is programmed to the gpio pin figure 5 gpio pin 5.5. sysclk output the sysclk pin outputs either the reference clock signal divided by a programmable power of two or the low power oscillator clock. division ratios from 1 to 1024 are possible. for divider ratios > 1 the duty cycle is 50%. bits sysclk[4:0] in the pinfuncsysclk register set the divider ratio. the sysclk output can be disabled. after power - up sysclk outputs 1/16 of the crystal oscillator clock, making it possible to use this clock to boot a micro - controller. 65 k ? vdd_io vdd_io output data input data enable weak pull-up enable output
circuit description www.onsemi.com AX5243 28 5.6. power - on - reset (por) AX5243 has an integrated power - on - reset block. no external por circuit is required. after por the AX5243 can be reset by first se tting the spi sel pin to high for at least 100 ns, then setting followed by resetting the bit rst in the pwrmode register. after por or reset all registers are set to their default values. 5.7. rf frequency generation subsystem the rf frequency generation subs ystem consists of a fully integrated synthesizer, which multiplies the reference frequency from the crystal oscillator to get the desired rf frequency. the advanced architecture of the synthesizer enables frequency resolutions of 1 hz, as well as fast sett ling times of 5 C 50 ? s depending on the settings (see section 4.3 : ac characteristics ). fast settling times mean fast start - up and fast rx/tx switching, which enables low - power system design. for receive operation the rf frequency is fed to the mixer, for transmit operation to the power - amplifier. the frequency must be programmed to the desired carrier frequency. the synthesizer loop bandwidth can be programmed, this serves three purposes: 1. start - up time optimization, s tart - up is faster for higher synthesizer loop bandwidths 2. tx spectrum optimization, phase - noise at 300 khz to 1 mhz distance from the carrier improves with lower synthesizer loop bandwidths 3. adaptation of the bandwidth to the data - rate. for transmission of f sk and msk it is required that the synthesizer bandwidth must be in the order of the data - rate. vco an on - chip vco converts the control voltage generated by the charge pump and loop filter into an output frequency. this frequency is used for transmit as w ell as for receive operation. the frequency can be programmed in 1 hz steps in the freq registers. for operation in the 433 mhz band, the rfdiv bit in the pllvcodiv register must be programmed. the fully integrated vco allows to operate the device in the frequency ranges 800 C 1050 mhz and 400 C 525 mhz. the carrier frequency range can be extended to 54 C 525 mhz and 27 C 262 mhz by using an appropriate external inductor between device pins l1 and l2. the bit vco2int in the pllvcodiv register must be set high to enter this mode.
circuit description w ww.onsemi.com AX5243 29 it is also possible to use a fully external vco by setting bits vco2int=0 and vcosel=1 in the pllvcodiv register. a differential input at a frequency of double the desired rf frequency must be input at device pins l1 and l2. the c ontrol voltage for the vco can be output at device pin filt when using external filter mode. the voltage range of this output pin is 0 C 1.8 v. this mode of operation is recommended for special applications where the phase noise requirements are not met w hen using the fully internal vco or the internal vco with external inductor. vco auto - ranging the AX5243 has an integrated auto - ranging function, which allows to set the correct vco range for specific frequency genera tion subsystem settings automatically. typically it has to be executed after power - up. the function is initiated by setting the rng_start bit in the pllranginga or pllrangingb register. the bit is readable and a 0 indicates the end of the ranging process. setting rng_start in the pllranginga register ranges the frequency in freqa , while setting rng_start in the pllrangingb register ranges the frequency in freqb . the rngerr bit indicates the correct execution of the auto - ranging. vco auto - ranging works with the fully integrated vco and with the internal vco with external inductor. loop filter and charge pump the AX5243 internal loop filter configuration together with the charge pump current sets the synthesizer loop ban d width. the internal loop - filter has three configurations that can be programmed via the register bits flt[1:0] in registers pllloop or pllloopboost the charge pump current can be programmed using register bits pllcpi[7:0] in registers pllcpi or pllcpiboo st . synthesizer bandwidths are typically 50 - 500 khz depending on the pllloop or pllloopboost settings, for details see the section 4.3 : ac characteristics . the a x5243 can be setup in such a way that when the synthesizer is started, the settings in the registers pllloopboost and pllcpiboost are applied first for a programmable duration before reverting to the settings in pllloop and pllcpi. this feature enables au tomated fastest start - up. setting bits flt[1:0]=00 bypasses the internal loop filter and the vco control voltage is output to an external loop filter at pin filt. this mode of operation is recommended for achieving lower bandwidths than with the internal l oop filter and for usage with a fully external vco.
circuit description www.onsemi.com AX5243 30 registers register bits purpose pllloop pllloopboost flt[1:0] synthesizer loop filter bandwidth and selection of external loop filter, recommended usage is to increase the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are possible. pllcpi pllcpiboost synthesizer charge pump current, recommended usage is to decrease the bandwidth (and improve the phase - noise) for low data - rate transmissions. pllvcodiv refdiv sets the synthesi zer reference divider ratio. rfdiv sets the synthesizer output divider ratio. vcosel selects either the internal or the external vco. vco2int selects either the internal vco inductor or an external inductor between pins l1 and l2. freqa, freqb prog ramming of the carrier frequency pllranginga, pllrangingb initiate vco auto - ranging and check results
circuit description w ww.onsemi.com AX5243 31 5.8. rf input and output stage (antp/antn) the AX5243 antenna interface uses differential pins antp and antn for both rx and tx. rx/tx switching is handled internally. lna the lna amplifies the differential rf signal from the antenna and buffers it to drive the i/q mixer. an external matching network is used to adapt the antenna impedance to the ic impedance. a dc feed to gnd must be provided at the antenna pins. for recommendations, see section 7 : applicat ion information . pa in tx mode the pa drives the signal generated by the frequency generation subsystem out to either the differential antenna terminals or to the single ended antenna pin. the antenna terminals are chosen via the bits txdiff and txse in register modecfga . the output power of the pa is programmed via the register txpwrcoeffb . the pa can be digit ally pre - distorted for high linearity. the output amplitude can be shaped (raised cosine), this mode is selected with bit amplshape in register modecfga. pa ramping is programmable in increments of the bit time and can be set to 1 C 8 bit times via bits s lowramp in register modecfga. output power as well as harmonic content will depend on the external impedance seen by the pa, recommendations are given in the section 7 : applicat ion information . 5.9. digit al if channel filter and demodulator the digital if channel filter and the demodulator extract the data bit - stream from the incoming if signal. they must be programmed to match the modulation scheme as well as the data - rate. inaccurate programming will lea d to loss of sensitivity. the channel filter offers bandwidths of 995 hz up to 221 khz. the axsem radiolab software calculates the necessary register settings for optimal performance and details can be found in the a x5243 programming manual . an overview of the registers involved is given in the following table as reference. the register setups typically must be done once at power - up of the device.
circuit description www.onsemi.com AX5243 32 registers register remarks decimation this register programs the band width of the digital channel filter. rxdatarate2 rxdatarate0 these registers specify the receiver bit rate, relative to the channel filter bandwidth. maxdroffset2maxdroffset0 these registers specify the maximum possible data rate offset. maxrfoffset2 maxrfoffset0 these registers specify the maximum possible rf frequency offset. timegain,drgain these registers specify the aggressiveness of the receiver bit timing recovery. more aggressive settings allow the receiver to synchronize with shorter preamble s, at the expense of more timing jitter and thus a higher bit error rate at a given signal - to - noise ratio. modulation this register selects the modulation to be used by the transmitter and the receiver, i.e. whether ask, fsk should be used. phasegain, f reqgaina, freqgainb, freqgainc, freqgaind, amplgain these registers control the bandwidth of the phase, frequency offset and amplitude tracking loops. agcgain this register controls the agc (automatic gain control) loop slopes, and thus the speed of gain adjustments. the faster the bit - rate, the faster the agc loop should be. txrate these registers control the bit rate of the transmitter. fskdev these registers control the frequency deviation of the transmitter in fsk mode. the receiver does not explicit ly need to know the frequency deviation, only the channel filter bandwidth has to be set wide enough for the complete modulation to pass.
cir cuit description w ww.onsemi.com AX5243 33 5.10. encoder the encoder is located between the framing unit, the demodulator and the modulator. it can optionally trans form the bit - stream in the following ways: ? it can invert the bit stream. ? it can perform differential encoding. this means that a zero is transmitted as no change in the level, and a one is transmitted as a change in the level. ? it can perform manchester en coding. manchester encoding ensures that the modulation has no dc content and enough transitions (changes from 0 to 1 and from 1 to 0) for the demodulator bit timing recovery to function correctly, but does so at a doubling of the data rate. ? it can perform spectral shaping (also know as whitening). spectral shaping removes dc content of the bit stream, ensures transitions for the demodulator bit timing recovery, and makes sure that the transmitted spectrum does not have discrete lines even if the transmitte d data is cyclic. it does so without adding additional bits, i.e. without changing the data rate. spectral shaping uses a self synchronizing feedback shift register. the encoder is programmed using the register encoding , details and recommendations on usag e are given in the AX5243 programming manual. 5.11. framing and fifo most radio systems today group data into packets. the framing unit is responsible for converting these packets into a bit - stream suitable for the modulat or, and to extract packets from the continuous bit - stream arriving from the demodulator. the framing unit supports two different modes: ? packet modes ? raw modes the micro - controller communicates with the framing unit through a 256 byte fifo. data in the fifo is organized in chunks. the chunk header encodes the length and what data is contained in the payload. chunks may contain packet data, but also rssi, frequency offset, timestamps, etc. the AX5243 contains one fifo. i ts direction is switched depending on whether transmit or receive mode is selected. the fifo can be operated in polled or interrupt driven modes. in polled mode, the micro - controller must periodically read the fifo status register or the fifo count registe r to determine whether the fifo needs servicing.
circuit description www.onsemi.com AX5243 34 in interrupt mode empty, not empty, full, not full and programmable level interrupts are provided. the AX5243 signals interrupts by asserting (driving high) its irq li ne. the interrupt line is level triggered, active high. interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or filling the fifo. basic fifo status (empty, full, overrun, underrun, fifo fill level above threshold, fifo fre e space above threshold) are also provided during each spi access on miso while the micro - controller shifts out the register address on mosi. see the spi interface section for details. this feature significantly reduces the number of spi accesses necessar y during transmit and receive. packet modes the AX5243 offers different packet modes. for arbitrary packet sizes hdlc is recommended since the flag and bit - stuffing mechanism. the AX5243 also offers packet modes with fixed packet length with a byte indicating the length of the packet. in packet modes a crc can be computed automatically. hdlc 1 mode is the main framing mode of the AX5243 . in this mode, the AX5243 performs automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (crc) field. the packet structure is given in the following table. flag address control information fcs (optional flag) 8 bit 8 bit 8 or 16 bit variable length, 0 or more bits in multiples of 8 16 / 32 bit 8 bit hdlc packets are delimited with flag sequences of content 0x7e. in ax5 243 the meaning of address and control is user defined. the frame check sequence (fcs) can be programmed to be crc - ccitt, crc - 16 or crc - 32. the receiver checks the crc, the result can be retrieved from the fifo, the crc is appended to the received data. i n wireless m - bus mode 2 , the packet structure is given in the following table. 1 note: hdlc mode follows high - level data link control (hdlc, iso 13239) protocol. 2 note: wireless m - bus mode follows en13757 - 4
circuit description w ww.onsemi.com AX5243 35 preamble l c m a fcs optional data block (optionally repeated with fcs) fcs variable 8 bit 8 bit 16 bit 48 bit 16 bit 8 C 96 bit 16 bit for details on implementing a hdlc comm unication as well as wireless m - bus please use the axsem radiolab software and see the AX5243 programming manual. raw modes in raw mode, the AX5243 does not perform any packet d elimiting or byte synchronization. it simply serializes transmit bytes and de - serializes the received bit - stream and groups it into bytes. this mode is ideal for implementing legacy protocols in software. raw mode with preamble match is similar to raw mode . in this mode, however, the receiver does not receive anything until it detects a user programmable bit pattern (called the preamble) in the receive bit - stream. when it detects the preamble, it aligns the de - serialization to it. the preamble can be betwee n 4 and 32 bits long. 5.12. rx agc and rssi AX5243 features three receiver signal strength indicators (rssi): 1. rssi before the digital if channel filter. the gain of the receiver is adjusted in order to keep the analog if filter output level inside the working range of the adc and demodulator. the register agccounter contains the current value of the agc and can be used as an rssi. the step size of this rssi is 0.625 db. the value can be used as soon as the rf frequency gen eration sub - system has been programmed. 2. rssi behind the digital if channel filter. the register rssi contains the current value of the rssi behind the digital if channel filter. the step size of this rssi is 1 db. 3. rssi behind the digital if channel filter high accuracy. the demodulator also provides amplitude information in the trk_amplitude register. by combining both the agccounter and the trk_amplitude registers, a high resolution (better than 0.1db) rssi value can be computed at the expense of a few ar ithmetic operations on the micro - controller. the axsem radiolab software calculates the necessary register settings for best performance and details can be found in the AX5243 programming manual .
circuit description www.onsemi.com AX5243 36 5.13. modulator dependin g on the transmitter settings the modulator generates various inputs for the pa: modulation bit = 0 bit = 1 main lobe bandwidth max. bitrate ask pa off pa on bw=bitrate 125 kbit/s fsk/msk/gfsk/gmsk ? f= - f deviation ? f=+f deviation bw=(1+h) ? bitrate 125 kbit /s psk ?? =0 0 ?? =180 0 bw=bitrate 125 kbit/s h = modulation index. it is the ratio of the deviation compared to the bit - rate; f deviation = 0.5 ? h ? bitrate, AX5243 can demodulate signals with h < 32. ask = amplitude s hift keying fsk = frequency shift keying msk = minimum shift keying; msk is a special case of fsk, where h = 0.5, and therefore f deviation = 0.25 ? bitrate; the advantage of msk over fsk is that it can be demodulated more robustly. psk = phase shift keyi ng all modulation schemes, except 4 - fsk, are binary. amplitude can be shaped using a raised cosine waveform. amplitude shaping will also be performed for constant amplitude modulation ((g)fsk, (g)msk) for ramping up and down the pa. amplitude shaping shoul d always be enabled. frequency shaping can either be hard (fsk, msk), or gaussian (gmsk, gfsk), with selectable bt=0.3 or bt=0.5. modulation dibit = 00 dibit = 01 dibit = 11 dibit = 10 main lobe bandwidth max. bitrate 4 - fsk ? f= - 3f deviation ? f= - f deviation ? ? f=+f deviation ? ? f=+3f deviation bw=(1+3h) ? bitrate 115.2 kbit/s 4 - fsk frequency shaping is always hard. 5.14. automatic frequency control (afc) the AX5243 features an automatic frequency tracking loop which is capable of tracking the transmitter frequency within the rx filter band width. on top of that the AX5243 has a frequency tracking register trkrffreq to synchronize the receiver frequency to a
circuit description w ww.onsemi.com AX5243 37 carrier signal. for afc adjustment, the frequency offset can be computed with the following formula: . the pull - in range of the afc can be programmed with the maxrfoffset registers. 5.15. pwrmode register the pwrmode register controls, which parts of the chip are operati ng. pwrmode register name description 0000 powerdown all digital and analog functions, except the register file, are disabled. the core supply voltages are switched off to conserve leakage power. register contents are preserved and accessible registers vi a spi, but at a slower speed. access to the fifo is not possible and the contents are not preserved. powerdown mode is only entered once the fifo is empty. 0001 deepsleep AX5243 is fully turned off. all digital and analog functions are disabled. all register contents are lost. to leave deepsleep mode the pin sel has to be pulled low. this will initiate startup and reset of the AX5243 . then the miso line should be polled, as it will be held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation. 0101 standby the crystal oscillator and the reference are powered on; receiver and transmitter are off. register cont ents are preserved and accessible registers via spi. access to the fifo is not possible and the contents are not preserved. standby is only entered once the fifo is empty. 0110 fifo the reference is powered on. register contents are preserved and accessib le registers via spi. access to the fifo is possible and the contents are preserved. 1000 synthrx the synthesizer is running on the receive frequency. transmitter and receiver are still off. this mode is used to let the synthesizer settle on the correct frequency for receive. 1001 fullrx synthesizer and receiver are running. 1011 wor receiver wakeup - on - radio mode. the mode the same as powerdown, but the 640 hz internal low power oscillator is running. 1100 synthtx the synthesizer is running on the tran smit frequency. transmitter and receiver are still off. this mode is used to let the synthesizer settle on the correct frequency for transmit. 1101 fulltx synthesizer and transmitter are running. do not switch into this mode before the synthesizer has com pletely settled on the transmit frequency (in synthtx mode), otherwise spurious spectral transmissions will occur. for the corresponding currents see table in section 4.2 . xtal f trkrffreq f 24 2 ? ?
circuit description www.onsemi.com AX5243 38 a typical pwrmode sequence for a transmit session : s tep pwrmode remarks 1 powerdown 2 standby the settling time is dominated by the crystal used, typical value 3ms. 3 fulltx data transmission 4 powerdown a typical pwrmode sequence for a receive session : step pwrmode[3:0] remarks 1 powerdown 2 st andby the settling time is dominated by the crystal used, typical value 3ms 3 fullrx data reception 4 powerdown
circuit description w ww.onsemi.com AX5243 39 5.16. serial peripheral interface (spi) the AX5243 can be programmed via a four wire serial interface ac cording spi using the pins clk, mosi, miso and sel. registers for setting up the AX5243 are programmed via the serial peripheral interface in all device modes. when the interface signal sel is pulled low, a configura tion data stream is expected on the input signal pin mosi, which is interpreted as d0...dx , a0...ax , r_n/w . data read from the interface appears on miso. figure 6 shows a write/read access to the interface. the data stream is built of an address byte including read/write information and a data byte. depending on the r_n/w bit and address bits a[6..0], data d[7..0] can be written via mosi or read at the pin miso . r_n/w = 0 means read mode, r_n/w = 1 means write mode. most registers a re 8 bits wide and accessed using the waveforms as detailed in figure 7 . the most important registers are at the beginning of the address space, i.e. at addresses less than 0x70. these registers can be accessed more efficiently us ing the short address form, which is detailed in figure 6 . some registers are longer than 8 bits. these registers can be accessed more quickly than by reading and writing individual 8 bit parts. this is illustrated in figure 8 . accesses are not limited by 16 bits either, reading and writing data bytes can be continued as long as desired. after each byte, the address counter is incremented by one. also, this access form works with long addresses. during the address phase of the access, the AX5243 outputs the most important status bits. this feature is designed to speed up the software decision on what to do in an interrupt handler. the status bits contain the following i nformation: spi bit cell status meaning / register bit 0 - 1 (when transitioning out of deep sleep mode, this bit transitions from 0 ? 1 when the power becomes ready) 1 s14 pll lock 2 s13 fifo over 3 s12 fifo under 4 s11 threshold free ( fifofree > fi fothresh ) 5 s10 threshold count ( fifocount > fifothresh ) 6 s9 fifo full 7 s8 fifo empty 8 s7 pwrgood (not brownout) 9 s6 pwr interrupt pending 10 s5 radio event pending 11 s4 xtal oscillator running 12 s3 wakeup interrupt pending
circuit description www.onsemi.com AX5243 40 13 s2 lposc inter rupt pending 14 s1 gpadc interrupt pending 15 s0 internal note: bit cells 8 - 15 (s7s0) are only available in two address byte spi access formats. spi timing figure 6 spi 8 bit read/write access wit h timing figure 7 spi 8 bit long address read/write access figure 8 spi 16 bit long read/write access tsh r/w sel clk mosi miso a6 a5 a4 a3 a2 a1 d7 a0 d6 d5 d4 d0 d1 d2 d3 d7 d6 d5 d4 d3 d2 d1 d0 s14 s13 s12 s11 s10 s9 s8 tssd tco tss tck tch tcl th ts tssz r/w sel clk mosi miso a6 a5 a4 a3 a2 a1 d7 a0 d6 d5 d4 d0 d1 d2 d3 d7 d6 d5 d4 d3 d2 d1 d0 s6 s5 s4 s3 s2 s1 s0 a11 a10 a9 a7 a8 s7 s14 s13 s12 s11 s10 s9 s8 r/w sel clk mosi miso d6 d5 d4 d3 d2 d1 d7 d0 d6 d5 d4 d0 d1 d2 d3 d7 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 d7 a0 d7 s14 s13 s12 s11 s10 s9 s8 a6 a5 a4
circuit description w ww.onsemi.com AX5243 41 5.17. general purpose adc (gpadc) the AX5243 features a general purpose adc. the adc input pins are gpadc1 and gpadc2. the adc converts the voltage difference between applied between pins gpadc1 and gpadc2. if pin gpadc2 is left open, the adc converts the difference between an internally generated value of 800 mv and the voltage applied at pin gpadc1. the gpadc can only be used if the receiver is disabled. to enable the gpadc write 1 to the gpadc13 bit in the gpadcctrl register. to start a single conversion, write 1 to the busy bit in the gpadcctrl register. then wait for the busy bit to clear, or the gpadc interrupt to be asserted. the gpadc interrupt is cleared by reading the result register gpadc13value . if continuous sampling is desired, set the cont bit in regis ter gpadcctrl . the desired sampling rate can be specified in the gpadcperiod register. 5.18. ?? dac one digital pin C tcxo_en C may be used as a ?? digital - to - analog converter. a simple rc lowpass filter is needed to smooth the output. the dac may be used to output rssi, many demodulator variables, or a constant value under software control.
register bank description www.onsemi.com AX5243 42 6. regis ter bank description this section describes the bits of the register bank as reference. the registers are grouped by functional block to facilitate programming. the axsem radiolab software calculates the necessary register settings for best performance and details can be found in the AX5243 programming manual . an r in the retention column means that this registers contents are not lost during power - down mode. no checks are made whether the programmed combination of bi ts makes sense! bit 0 is always the lsb. note whole registers or register bits marked as reserved should be kept at their default values. note all addresses not documented here must not be accessed, neither in reading nor in writing. note the retention co lumn indicates if the register contents are preserved in power - down mode.
register bank description www.onsemi.com AX5243 43 6.1. control register map add name dir re t reset bit description 7 6 5 4 3 2 1 0 revision & interface probing 000 revision r r 01010001 siliconrev(7:0) silicon revision 001 scratch rw r 11000101 scratch(7:0) scratch register operating mode 002 pwrmode rw r 011 C 0000 rst xoen refen wds pwrmode(3:0) power mode voltage regulator 003 powstat r r CCCCCCCC ssum sref svref svana svmodem sbevana sbevmodem svio power managemen t status 004 powstickystat r r CCCCCCCC sssum sref ssvref ssvana ssvmodem ssbevana ssbevmodem ssvio power management sticky status 005 powirqmask rw r 00000000 mpwr good msref msvref ms vana ms vmodem msbe vana msbe vmodem msvio power management interrup t mask interrupt control 006 irqmask1 rw r CC 000000 C C irqmask(13:8) irq mask 007 irqmask0 rw r 00000000 irqmask(7:0) irq mask 008 radioeventmask1 rw r CCCCCCC 0 C C C C C C C radio event mask(8) radio event mask 009 radioeventmask0 rw r 00000000 radi o event mask(7:0) radio event mask 00a irqinversion1 rw r CC 000000 C C irqinversion(13:8) irq inversion 00b irqinversion0 rw r 00000000 irqinversion(7:0) irq inversion 00c irqrequest1 r r CCCCCCCC C C irqrequest(13:8) irq request 00d irqrequest0 r r CC CCCCCC irqrequest(7:0) irq request 00e radioeventreq1 r CCCCCCCC C C C C C C C radio event req(8) radio event request 00f radioeventreq0 r CCCCCCCC radio event req(7:0) radio event request modulation & framing 010 modulation rw r CCC 01000 C C C rx half modulation(3:0) modulation
register bank de scription www.onsemi.com AX5243 44 speed 011 encoding rw r CCC 00010 C C C enc nosync enc manch enc scram enc diff enc inv encoder/decoder settings 012 framing rw r C 0000000 frmrx crcmode(2:0) frmmode(2:0) fabort framing settings 014 crcinit3 rw r 11111111 crcinit(31:24) crc initialisation data 015 crcinit2 rw r 11111111 crcinit(23:16) crc initialisation data 016 crcinit1 rw r 11111111 crcinit(15:8) crc initialisation data 017 crcinit0 rw r 11111111 crcinit(7:0) crc initialisation data forward error corr ection 018 fec rw r 00000000 short mem rstvi terbi fec neg fec pos fecinpshift(2:0) fec ena fec (viterbi) configuration 019 fecsync rw r 01100010 fecsync(7:0) interleaver synchronisation threshold 01a fecstatus r r CCCCCCCC fec inv maxmetric(6:0) fec st atus status 01c radiostate r C CCCC 0000 C C C C radiostate(3:0) radio controller state 01d xtalstatus r r CCCCCCCC C C C C C C C xtal run crystal oscillator status pin configuration 020 pinstate r r CCCCCCCC C C ps pwr amp ps ant sel ps irq ps data ps dclk ps sys clk pinstate 021 pinfuncsysclk rw r 0 CC 01000 pu sysclk C C pfsysclk(4:0) sysclk pin function 022 pinfuncdclk rw r 00 CCC 100 pu dclk pi dclk C C C pfdclk(2:0) dclk pin function 023 pinfuncdata rw r 10 CCC 111 pu data pi data C C C pfdata(2:0) d ata pin function 024 pinfuncirq rw r 00 CCC 011 pu irq pi irq C C C pfirq(2:0) irq pin function 026 pinfunctcxo_en rw r 00 CC 0110 pu tcxo_en pi tcxo_en C C tcxo_en (3:0) tcxo_en pin function 027 pwramp rw r CCCCCCC 0 C C C C C C C pwramp pwramp control fif o 028 fifostat r r 0 CCCCCCC fifo auto commit C fifo free thr fifo cnt thr fifo over fifo under fifo full fifo empty fifo control w r fifocmd(5:0)
register bank description www.onsemi.com AX5243 45 029 fifodata rw CCCCCCCC fifodata(7:0) fifo data 02a fifocount1 r r CCCCCCC 0 C C C C C C C fif o count( 8) number of words currently in fifo 02b fifocount0 r r 00000000 fifocount(7:0) number of words currently in fifo 02c fifofree1 r r CCCCCCC 1 C C C C C C C fifo free(8) number of words that can be written to fifo 02d fifofree0 r r 00000000 fifofr ee(7:0) number of words that can be written to fifo 02e fifothresh1 rw r CCCCCCC 0 C C C C C C C fifo thresh (8) fifo threshold 02f fifothresh0 rw r 00000000 fifothresh(7:0) fifo threshold synthesizer 030 pllloop rw r 0 CCC 1001 freqb C C C direct filt en flt(1:0) pll loop filter settings 031 pllcpi rw r 00001000 pllcpi pll charge pump current (boosted) 032 pllvcodiv rw r C 000 C 000 C vcoi man vco2int vcosel C rfdiv refdiv(1:0) pll divider settings 033 pllranginga rw r 00001000 sticky lock pll lock rngerr rng start vcora(3:0) pll autoranging 034 freqa3 rw r 00111001 freqa(31:24) synthesizer frequency 035 freqa2 rw r 00110100 freqa(23:16) synthesizer frequency 036 freqa1 rw r 11001100 freqa(15:8) synthesizer frequency 037 freqa0 rw r 11001101 freqa(7:0) synthesizer frequency 038 pllloopboost rw r 0 CCC 1011 freqb C C C direct filt en flt(1:0) pll loop filter settings (boosted) 039 pllcpiboost rw r 11001000 pllcpi pll charge pump current 03b pllrangingb rw r 00001000 sticky lock pll lock rngerr rng start vcorb(3:0) pll autoranging 03c freqb3 rw r 00111001 freqb(31:24) synthesizer frequency 03d freqb2 rw r 00110100 freqb(23:16) synthesizer frequency 03e freqb1 rw r 11001100 freqb(15:8) synthesizer frequency 03f freqb0 rw r 11001101 freqb(7:0) synthesize r frequency signal strength 040 rssi r r CCCCCCCC rssi(7:0) received signal strength indicator
register bank description www.onsemi.com AX5243 46 041 bgndrssi rw r 00000000 bgndrssi(7:0) background rssi 042 diversity rw r CCCCCC 00 C C C C C C ant sel div ena antenna diversity configuration 043 agccoun ter rw r CCCCCCCC agccounter(7:0) agc current value receiver tracking 045 trkdatarate2 r r CCCCCCCC trkdatarate(23:16) datarate tracking 046 trkdatarate1 r r CCCCCCCC trkdatarate(15:8) datarate tracking 047 trkdatarate0 r r CCCCCCCC trkdatarate(7:0) da tarate tracking 048 trkampl1 r r CCCCCCCC trkampl(15:8) amplitude tracking 049 trkampl0 r r CCCCCCCC trkampl(7:0) amplitude tracking 04a trkphase1 r r CCCCCCCC C C C C trkphase(11:8) phase tracking 04b trkphase0 r r CCCCCCCC trkphase(7:0) phase trackin g 04d trkrffreq2 rw r CCCCCCCC C C C C trrfkfreq(19:16) rf frequency tracking 04e trkrffreq1 rw r CCCCCCCC trrfkfreq(15:8) rf frequency tracking 04f trkrffreq0 rw r CCCCCCCC trrfkfreq(7:0) rf frequency tracking 050 trkfreq1 rw r CCCCCCCC trkfreq(15:8) frequency tracking 051 trkfreq0 rw r CCCCCCCC trkfreq(7:0) frequency tracking 052 trkfskdemod1 r r CCCCCCCC C C trkfskdemod(13:8) fsk demodulator tracking 053 trkfskdemod0 r r CCCCCCCC trkfskdemod(7:0) fsk demodulator tracking 054 trkafskdemod1 r r CCC CCCCC trkafskdemod(15:8) afsk demodulator tracking 055 trkafskdemod0 r r CCCCCCCC trkafskdemod(7:0) afsk demodulator tracking timer 059 timer2 r C CCCCCCCC timer(23:16) 1mhz timer 05a timer1 r C CCCCCCCC timer(15:8) 1mhz timer 05b timer0 r C CCCCCCCC timer(7:0) 1mhz timer wakeup timer 068 wakeuptimer1 r r CCCCCCCC wakeuptimer(15:8) wakeup timer 069 wakeuptimer0 r r CCCCCCCC wakeuptimer(7:0) wakeup timer 06a wakeup1 rw r 00000000 wakeup(15:8) wakeup time 06b wakeup0 rw r 00000000 wakeup(7:0) wakeup time
register bank description www.onsemi.com AX5243 47 06c wakeupfreq1 rw r 00000000 wakeupfreq(15:8) wakeup frequency 06d wakeupfreq0 rw r 00000000 wakeupfreq(7:0) wakeup frequency 06e wakeupxoearly rw r 00000000 wakeupxoearly wakeup crystal oscillator early physical layer parameters receiver param eters 100 iffreq1 rw r 00010001 iffreq(15:8) 2nd lo / if frequency 101 iffreq0 rw r 00100111 iffreq(7:0) 2nd lo / if frequency 102 decimation rw r C 0001101 C decimation(6:0) decimation factor 103 rxdatarate2 rw r 00000000 rxdatarate(23:16) receiver dat arate 104 rxdatarate1 rw r 00111101 rxdatarate(15:8) receiver datarate 105 rxdatarate0 rw r 10001010 rxdatarate(7:0) receiver datarate 106 maxdroffset2 rw r 00000000 maxdroffset(23:16) maximum receiver datarate offset 107 maxdroffset1 rw r 00000000 max droffset(15:8) maximum receiver datarate offset 108 maxdroffset0 rw r 10011110 maxdroffset(7:0) maximum receiver datarate offset 109 maxrfoffset2 rw r 0 CCC 0000 freq offs corr C C C maxrfoffset(19:16) maximum receiver rf offset 10a maxrfoffset1 rw r 0001 0110 maxrfoffset(15:8) maximum receiver rf offset 10b maxrfoffset0 rw r 10000111 maxrfoffset(7:0) maximum receiver rf offset 10c fskdmax1 rw r 00000000 fskdevmax(15:8) four fsk rx deviation 10d fskdmax0 rw r 10000000 fskdevmax(7:0) four fsk rx deviation 10e fskdmin1 rw r 11111111 fskdevmin(15:8) four fsk rx deviation 10f fskdmin0 rw r 10000000 fskdevmin(7:0) four fsk rx deviation 110 afskspace1 rw r CCCC 0000 C C C C afskspace(11:8) afsk space (0) frequency 111 afskspace0 rw r 01000000 afskspace(7:0) afsk space (0) frequency 112 afskmark1 rw r CCCC 0000 C C C C afskmark(11:8) afsk mark (1) frequency 113 afskmark0 rw r 01110101 afskmark(7:0) afsk mark (1) frequency 114 afskctrl rw r CCC 00100 C C C afskshift0(4:0) afsk control 115 amplfilter rw r CCCC 0000 C C C C amplfilter(3:0) amplitude filter 116 frequencyleak rw r CCCC 0000 C C C C frequencyleak[3:0] baseband frequency recovery loop leakiness
register bank description www.onsemi.com AX5243 48 117 rxparamsets rw r 00000000 rxps3(1:0) rxps2(1:0) rxps1(1:0) rxps0(1:0) receiver parameter set indirecti on 118 rxparamcurset r r CCCCCCCC C C C rxsi(2) rxsn(1:0) rxsi(1:0) receiver parameter current set receiver parameter set 0 120 agcgain0 rw r 10110100 agcdecay0(3:0) agcattack0(3:0) agc speed 121 agctarget0 rw r 01110110 agctarget0(7:0) agc target 122 agcahyst0 rw r CCCCC 000 - agcahyst0(2:0) agc digital threshold range 123 agcminmax0 rw r C 000 C 000 - agcmaxda0(2:0) - agcminda0(2:0) agc digital min/max set points 124 timegain0 rw r 11111000 timegain0m timegain0e timing gain 125 drgain0 rw r 11110010 d rgain0m drgain0e data rate gain 126 phasegain0 rw r 11 CC 0011 filteridx0(1:0) C C phasegain0(3:0) filter index, phase gain 127 freqgaina0 rw r 00001111 freq lim0 freq modulo0 freq halfmod 0 freq ampl gate0 freqgaina0(3:0) frequency gain a 128 freqgainb0 r w r 00 C 11111 freq freeze0 freq avg0 C freqgainb0(4:0) frequency gain b 129 freqgainc0 rw r CCC 01010 C C C freqgainc0(4:0) frequency gain c 12a freqgaind0 rw r 0 CC 01010 rffreq freeze0 C C freqgaind0(4:0) frequency gain d 12b amplgain0 rw r 01 CC 0110 ampl avg ampl agc C C amplgain0(3:0) amplitude gain 12c freqdev10 rw r CCCC 0000 C C C C freqdev0(11:8) receiver frequency deviation 12d freqdev00 rw r 00100000 freqdev0(7:0) receiver frequency deviation 12e fourfsk0 rw r CCC 10110 C C C dev update0 devdecay0( 3:0) four fsk control 12f bboffsres0 rw r 10001000 resintb0(3:0) resinta0(3:0) baseband offset compensation resistors receiver parameter set 1 130 agcgain1 rw r 10110100 agcdecay1(3:0) agcattack1(3:0) agc speed 131 agctarget1 rw r 01110110 agctarget1(7 :0) agc target 132 agcahyst1 rw r CCCCC 000 - agcahyst1(2:0) agc digital threshold range 133 agcminmax1 rw r C 000 C 000 - agcmaxda1(2:0) - agcminda1(2:0) agc digital min/max set points 134 timegain1 rw r 11110110 timegain1m timegain1e timing gain 135 drga in1 rw r 11110001 drgain1m drgain1e data rate gain
register bank description www.onsemi.com AX5243 49 136 phasegain1 rw r 11 CC 0011 filteridx1(1:0) C C phasegain1(3:0) filter index, phase gain 137 freqgaina1 rw r 00001111 freq lim1 freq modulo1 freq halfmod 1 freq ampl gate1 freqgaina1(3:0) frequency gain a 138 freqgainb1 rw r 00 C 11111 freq freeze1 freq avg1 C freqgainb1(4:0) frequency gain b 139 freqgainc1 rw r CCC 01011 C C C freqgainc1(4:0) frequency gain c 13a freqgaind1 rw r 0 CC 01011 rffreq freeze1 C C freqgaind1(4:0) frequency gain d 13b amplgain1 rw r 01 CC 0110 ampl avg1 ampl1 agc1 C C amplgain1(3:0) amplitude gain 13c freqdev11 rw r CCCC 0000 C C C C freqdev1(11:8) receiver frequency deviation 13d freqdev01 rw r 00100000 freqdev1(7:0) receiver frequency deviation 13e fourfsk1 rw r CCC 11000 C C C dev update1 devdecay1(3:0) four fsk control 13f bboffsres1 rw r 10001000 resintb1(3:0) resinta1(3:0) baseband offset compensation resistors receiver parameter set 2 140 agcgain2 rw r 11111111 agcdecay2(3:0) agcattack2(3:0) agc speed 141 agctarget2 rw r 01110110 agctarget2(7:0) agc target 142 agcahyst2 rw r CCCCC 000 - agcahyst2(2:0) agc digital threshold range 143 agcminmax2 rw r C 000 C 000 - agcmaxda2(2:0) - agcminda2(2:0) agc digital min/max set points 144 timegain2 rw r 11110101 timegain2m timegain2e timing gain 145 drgain2 rw r 11110000 drgain2m drgain2e data rate gain 146 phasegain2 rw r 11 CC 0011 filteridx2(1:0) C C phasegain2(3:0) filter index, phase gain 147 freqgaina2 rw r 00001111 freq lim2 freq modulo2 freq halfmod 2 freq ampl gate2 freqgaina 2(3:0) frequency gain a 148 freqgainb2 rw r 00 C 11111 freq freeze2 freq avg2 C freqgainb2(4:0) frequency gain b 149 freqgainc2 rw r CCC 01101 C C C freqgainc2(4:0) frequency gain c 14a freqgaind2 rw r 0 CC 01101 rffreq freeze2 C C freqgaind2(4:0) frequency gain d 14b amplgain2 rw r 01 CC 0110 ampl avg2 ampl agc2 C C amplgain2(3:0) amplitude gain
register bank description www.onsemi.com AX5243 50 14c freqdev12 rw r CCCC 0000 C C C C freqdev2(11:8) receiver frequency deviation 14d freqdev02 rw r 00100000 freqdev2(7:0) receiver frequency deviation 14e fourfsk2 rw r CCC 11010 C C C dev update2 devdecay2(3:0) four fsk control 14f bboffsres2 rw r 10001000 resintb2(3:0) resinta2(3:0) baseband offset compensation resistors receiver parameter set 3 150 agcgain3 rw r 11111111 agcdecay3(3:0) agcattack3(3:0) agc speed 151 agctarget3 rw r 01110110 agctarget3(7:0) agc target 152 agcahyst3 rw r CCCCC 000 - agcahyst3(2:0) agc digital threshold range 153 agcminmax3 rw r C 000 C 000 - agcmaxda3(2:0) - agcminda3(2:0) agc digital min/max set points 154 timegain3 rw r 11110101 timegain3m timegain3e timing gain 155 drgain3 rw r 11110000 drgain3m drgain3e data rate gain 156 phasegain3 rw r 11 CC 0011 filteridx3(1:0) C C phasegain3(3:0) filter index, phase gain 157 freqgaina3 rw r 00001111 freq lim3 freq modulo3 freq halfmod 3 freq ampl gate3 freqgaina3(3:0) frequency gain a 158 freqgainb3 rw r 00 C 11111 freq freeze3 freq avg3 C freqgainb3(4:0) frequency gain b 159 freqgainc3 rw r CCC 01101 C C C freqgainc3(4:0) frequency gain c 15a freqgaind3 rw r 0 CC 01101 rffreq freeze3 C C freqg aind3(4:0) frequency gain d 15b amplgain3 rw r 01 CC 0110 ampl avg3 ampl agc3 C C amplgain3(3:0) amplitude gain 15c freqdev13 rw r CCCC 0000 C C C C freqdev3(11:8) receiver frequency deviation 15d freqdev03 rw r 00100000 freqdev3(7:0) receiver frequency de viation 15e fourfsk3 rw r CCC 11010 C C C dev update3 devdecay3(3:0) four fsk control 15f bboffsres3 rw r 10001000 resintb3(3:0) resinta3(3:0) baseband offset compensation resistors transmitter parameters 160 modcfgf rw r CCCCCC 00 C C C C C C freq shape modulator configuration f 161 fskdev2 rw r 00000000 fskdev(23:16) fsk frequency deviation
register bank description www.onsemi.com AX5243 51 162 fskdev1 rw r 00001010 fskdev(15:8) fsk frequency deviation 163 fskdev0 rw r 00111101 fskdev(7:0) fsk frequency deviation 164 modcfga rw r 0000 C 101 brown gate pttlck gate slow ramp C ampl shape tx se tx diff modulator configuration a 165 txrate2 rw r 00000000 txrate(23:16) transmitter bitrate 166 txrate1 rw r 00101000 txrate(15:8) transmitter bitrate 167 txrate0 rw r 11110110 txrate(7:0) transmitter bitrate 168 txpwrcoeffa1 rw r 00000000 txpwrcoeffa(15:8) transmitter predistortion coefficient a 169 txpwrcoeffa0 rw r 00000000 txpwrcoeffa(7:0) transmitter predistortion coefficient a 16a txpwrcoeffb1 rw r 00001111 txpwrcoeffb(15:8) transmitter predistortion c oefficient b 16b txpwrcoeffb0 rw r 11111111 txpwrcoeffb(7:0) transmitter predistortion coefficient b 16c txpwrcoeffc1 rw r 00000000 txpwrcoeffc(15:8) transmitter predistortion coefficient c 16d txpwrcoeffc0 rw r 00000000 txpwrcoeffc(7:0) transmitter pre distortion coefficient c 16e txpwrcoeffd1 rw r 00000000 txpwrcoeffd(15:8) transmitter predistortion coefficient d 16f txpwrcoeffd0 rw r 00000000 txpwrcoeffd(7:0) transmitter predistortion coefficient d 170 txpwrcoeffe1 rw r 00000000 txpwrcoeffe(15:8) tr ansmitter predistortion coefficient e 171 txpwrcoeffe0 rw r 00000000 txpwrcoeffe(7:0) transmitter predistortion coefficient e pll parameters 180 pllvcoi rw r 0 C 010010 vcoie C vcoi(5:0) vco current 181 pllvcoir rw r CCCCCCCC C C vcoir(5:0) vco current r eadback 182 plllockdet rw r CCCCC 011 lockdetdlyr C C C lock det dlym lockdetdly pll lock detect delay 183 pllrngclk rw r CCCCC 011 C C C C C pllrngclk(2:0) pll ranging clock crystal oscillator 184 xtalcap rw r 00000000 xtalcap(7:0) crystal oscillator lo ad capacitance baseband 188 bbtune rw r CCC 01001 C C C bb tune run bbtune(3:0) baseband tuning 189 bboffscap rw r C 111 C 111 C cap int b(2:0) C cap int a(2:0) baseband offset compensation capacitors
register bank description www.onsemi.com AX5243 52 mac layer parameters packet format 200 pktaddrcfg rw r 001 C 0000 msb first crc skip first fec sync dis C addr pos(3:0) packet address config 201 pktlencfg rw r 00000000 len bits(3:0 len pos(3:0) packet length config 202 pktlenoffset rw r 00000000 len offset(7:0) packet length offset 203 pktmaxlen rw r 0000 0000 max len(7:0) packet maximum length 204 pktaddr3 rw r 00000000 addr(31:24) packet address 3 205 pktaddr2 rw r 00000000 addr(23:16) packet address 2 206 pktaddr1 rw r 00000000 addr(15:8) packet address 1 207 pktaddr0 rw r 00000000 addr(7:0) packet a ddress 0 208 pktaddrmask3 rw r 00000000 addrmask(31:24) packet address mask 1 209 pktaddrmask2 rw r 00000000 addrmask(23:16) packet address mask 0 20a pktaddrmask1 rw r 00000000 addrmask(15:8) packet address mask 1 20b pktaddrmask0 rw r 00000000 addrma sk(7:0) packet address mask 0 pattern match 210 match0pat3 rw r 00000000 match0pat(31:24) pattern match unit 0, pattern 211 match0pat2 rw r 00000000 match0pat(23:16) pattern match unit 0, pattern 212 match0pat1 rw r 00000000 match0pat(15:8) pattern mat ch unit 0, pattern 213 match0pat0 rw r 00000000 match0pat(7:0) pattern match unit 0, pattern 214 match0len rw r 0 CC 00000 match0 raw C C match0len pattern match unit 0, pattern length 215 match0min rw r CCC 00000 C C C match0min pattern match unit 0, mini mum match 216 match0max rw r CCC 11111 C C C match0max pattern match unit 0, maximum match 218 match1pat1 rw r 00000000 match1pat(15:8) pattern match unit 1, pattern 219 match1pat0 rw r 00000000 match1pat(7:0) pattern match unit 1, pattern 21c match1len rw r 0 CCC 0000 match1 raw C C C match1len pattern match unit 1, pattern length 21d match1min rw r CCCC 0000 C C C C match1min pattern match unit 1, minimum match 21e match1max rw r CCCC 1111 C C C C match1max pattern match unit 1, maximum match packet con troller
register bank description www.onsemi.com AX5243 53 220 tmgtxboost rw r 00110010 tmgtxbooste tmgtxboostm transmit pll boost time 221 tmgtxsettle rw r 00001010 tmgtxsettlee tmgtxsettlem transmit pll (post boost) settling time 223 tmgrxboost rw r 00110010 tmgrxbooste tmgrxboostm receive pll boost t ime 224 tmgrxsettle rw r 00010100 tmgrxsettlee tmgrxsettlem receive pll (post boost) settling time 225 tmgrxoffsacq rw r 01110011 tmgrxoffsacqe tmgrxoffsacqm receive baseband dc offset acquisition time 226 tmgrxcoarseagc rw r 00111001 tmgrxcoarseagce tm grxcoarseagcm receive coarse agc time 227 tmgrxagc rw r 00000000 tmgrxagce tmgrxagcm receiver agc settling time 228 tmgrxrssi rw r 00000000 tmgrxrssie tmgrxrssim receiver rssi settling time 229 tmgrxpreamble1 rw r 00000000 tmgrxpreamble1e tmgrxpreamble1 m receiver preamble 1 timeout 22a tmgrxpreamble2 rw r 00000000 tmgrxpreamble2e tmgrxpreamble2m receiver preamble 2 timeout 22b tmgrxpreamble3 rw r 00000000 tmgrxpreamble3e tmgrxpreamble3m receiver preamble 3 timeout 22c rssireference rw r 00000000 rssir eference rssi offset 22d rssiabsthr rw r 00000000 rssiabsthr rssi absolute threshold 22e bgndrssigain rw r CCCC 0000 C C C C bgndrssigain background rssi averaging time constant 22f bgndrssithr rw r CC 000000 C C bgndrssithr background rssi relative thres hold 230 pktchunksize rw r CCCC 0000 C C C C pktchunksize(3:0) packet chunk size 231 pktmiscflags rw r CCC 00000 C C C wor multi pkt agc settl det bgnd rssi rxagc clk rxrssi clk packet controller miscellaneous flags 232 pktstoreflags rw r C 0000000 C st an t rssi st crcb st rssi st dr st rfoffs st foffs st timer packet controller store flags 233 pktacceptflags rw r CC 000000 C C accpt lrgp accpt szf accpt addrf accpt crcf accpt abrt accpt residu e packet controller accept flags special functions general pur pose adc 300 gpadcctrl rw r CC 000000 busy C 0 0 0 gpadc13 cont ch isol general purpose adc control 301 gpadcperiod rw r 00111111 gpadcperiod(7:0) gpadc sampling period 308 gpadc13value1 r CCCCCCCC C C C C C C gpadc13value(9:8) gpadc13 value
re gister bank description www.onsemi.com AX5243 54 309 gpadc 13value0 r CCCCCCCC gpadc13value(7:0) gpadc13 value low power oscillator calibration 310 lposcconfig rw 00000000 lposc osc invert lposc osc double lposc calibr lposc calibf lposc irqr lposc irqf lposc fast lposc ena low power oscillator configuration 31 lposcstatus r CCCCCCCC C C C C C C lposc irq lposc edge low power oscillator status 312 lposckfilt1 rw 00100000 lposckfilt(15:8) low power oscillator calibration filter constant 313 lposckfilt0 rw 11000100 lposckfilt(7:0) low power oscillator calibration filter constant 314 lposcref1 rw 01100001 lposcref(15:8) low power oscillator calibration reference 315 lposcref0 rw 10101000 lposcref(7:0) low power oscillator calibration reference 316 lposcfreq1 rw 00000000 lposcfreq(9:2) low power oscillator calibration frequency 317 lposcfreq0 rw 0000 CCCC lposcfreq(1: - 2) C C C C low power oscillator calibration frequency 318 lposcper1 rw CCCCCCCC lposcper(15:8) low power oscillator calibration period 319 lposcper0 rw CCCCCCCC lposcper(7:0) low power oscillator calibration period dac 330 dacvalue1 rw r CCCC 0000 C C C C dacvalue(11:8) dac value 331 dacvalue2 rw r 00000000 dacvalue(7:0) dac value 332 dacconfig rw r 00 CC 0000 dac pwm dac clk x2 C C dacinput(3:0) dac configuration
application information www.onsemi.com AX5243 55 55 7. applicat ion information 7.1. typical application diagrams match to 50 ohm for the antenna pins (868/915/433/169 mhz rx/tx operation) figure 9 structure of the antenna interface for tx/rx operation to 50 ? frequency band lc1,2 [nh] cc1,2 [pf] ct1,2 [pf] lt1,2 [nh] cm1 [pf] cm2 [pf] lb1,2 [nh] cb2 [pf] cf [pf] optional lf [nh] optional ca [pf] optional 868 / 915 mhz 18 nc 2.7 18 6.2 3.6 12 2.7 nc 0 ohm nc 433 mhz 100 nc 4.3 43 11 5. 6 27 5.1 nc 0 ohm nc 470 mhz 100 nc 3.9 33 4.7 nc 22 4.7 nc 0 ohm nc 169 mhz 150 10 10 120 12 nc 68 12 6.8 30 27 50 ?? single - ended equipment or antenna ic antenna pins lt1 lc1 lb1 ct1 cc1 cm1 lt 2 lc2 ct2 cc2 cm2 cb2 lb2 cf lf ca ca optional filter stage to suppress tx harmonics
application information www.onsemi.com AX5243 56 using a dipole antenna and the internal tx/rx switch figure 10 typical application diagram with dipole antenna and internal tx/rx switch vdd_ana gnd antp antn vdd_ana clk16p clk16n gpadc2 gpadc1 vdd_io tcxo_en irq mosi miso clk filt l2 l1 sysclk sel microcontroller AX5243
application information www.onsemi.com AX5243 57 57 using a single - ended antenna and the internal tx/rx switch figure 11 typical application d iagram with single - ended antenna and internal tx/rx switch vdd_ana gnd antp antn vdd_ana clk16p clk16n gpadc2 gpadc1 vdd_io tcxo_en irq mosi miso clk filt l2 l1 sysclk sel microcontroller AX5243 50 ohm
application information www.onsemi.com AX5243 58 using an external vco inductor figure 12 typical application diagram with external vco inductor vdd_ana gnd antp antn vdd_ana clk16p clk16n gpadc2 gpadc1 vdd_io tcxo_en irq mosi miso clk filt l2 l1 sysclk sel microcontroller AX5243 lvco
application information www.onsemi.com AX5243 59 59 using an external vco figure 13 typical application diagram with external vco vdd_ana gnd antp antn vdd_ana clk16p clk16n gpadc2 gpadc1 vdd_io tcxo_en (gpio) irq mosi miso clk filt l2 l1 sysclk sel microcontroller AX5243 vctrl outp outn en vco
application information www.onsemi.com AX5243 60 using a tcxo note 1: for detailed tcxo network recommendations depending on tcxo output swing refer to the AX5243 application note: use with a txco reference clock. figure 14 typical application diagram with a tcxo vdd_ana gnd antp antn vdd_ana clk16p clk16n gpadc2 gpadc1 vdd_io tcxo_en irq mosi miso clk filt l2 l1 sysclk sel microcontroller AX5243 tcxo c1_tcxo 1 c2_tcxo 1 en_tcxo
qfn28 package information www.onsemi.com AX5243 61 61 8. qfn28 package information 8.1. package outline qfn20 4 mm x 4 mm notes 1. awl yyww is the packaging lot code 2. rohs AX5243 - 1 awlyyww
qfn28 package information www.onsemi.com AX5243 62 8.2. qfn28 solderi ng profile profile feature pb - free process average ramp - up rate 3 c/sec max. preheat preheat temperature min t smin 150c temperature max t smax 200c time (t smin to t smax ) t s 60 C 180 sec time 25c to peak temperature t 25 to peak 8 min max. reflow phase liquidus temperature t l 217c time over liquidus temperature t l 60 C 150 sec peak temperature t p 260c time within 5c of actual peak temperature t p 20 C 40 sec cooling phase ramp - down rate 6c/sec max. notes: all temperatures refer to the top side of the package, measured on the package body surface. time t p t l t sma x t smi n t 25 to peak t s t l 25c preheat reflow cooling t p temperatu re
qfn28 package information www.onsemi.com AX5243 63 63 8.3. qfn28 recommended pad layout 1. pcb land and solder masking recommendations are shown in figure 15 . figure 15 : pcb land and solder mask recommendations 2. thermal vias should be used on the pcb thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the p rinted circuit board. the number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 3. increasing the number of vias through the printed circuit board will improve the thermal conductivity to the revers e side ground plane and external heat sink. in general, adding more metal through the pc board under the ic will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. 8.4. assembly process stencil design & solder paste application 1. stainless steel stencils are recommended for solder paste application. 2. a stencil thickness of 0.125 C 0.150 mm (5 C 6 mils) is recommended for screening. 3. for the pcb thermal pad, solder paste should be printed on the pc b by designing a stencil with an array of smaller openings that sum to 50% of the qfn exposed pad area. solder paste should be applied through an array of squares (or circles) as shown in figure 16 . 4. the aperture opening for the signal pads should be between 50 - 80% of the qfn pad area as shown in figure 17 . 5. optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. a = clearance from pcb thermal pad to solder mask opening, 0.0635 mm minimum b = clearance from edge of pcb thermal pad to pcb land, 0.2 mm minimum c = clearance from pcb land edge to solder mask opening to be as tight as possible to ensure that some s older mask remains between pcb pads d = pcb land length = qfn solder pad length + 0.1mm e = pcb land width = qfn solder pad width + 0.1 mm
qfn28 package information www.onsemi.com AX5243 64 6. the fine pitch of the ic leads requir es accurate alignment of the stencil and the printed circuit board. the stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 7. no - clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water - soluble flux is used. figure 16 : solder paste application on exposed pad minimum 50% cov er age 62% cove ra ge maximum 80% coverage figure 17 : solder paste appli cation on pins
www.onsemi.com AX5243 65 65

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